Project Title: LFSR based Pseudorandom Pattern Generator for MEMS
Current strides in programmable logic thickness, speed and description that is equipment have actually really empowered the engineer having the power to implement superior functionality that is electronic industry field programmable gate array (FPGA). Linear feedback shift resister (LFSR) became one of the elements which are central in evaluating and self testing of contemporary complex systems which can be electronic processors, controllers and built-in circuits. This project presents the FPGA implementation of an LFSR based pseudo random pattern generator. This LFSR has the characteristics of high speed, low power usage also it's particularly matched in processing environment where constant circulation random figures are expected. A software that is normal the pattern generator considered in this work may be the screening of micro-electro-mechanical-system (MEMS), where power that is low is required. VHDL was in fact employed to implement the LFSR on FPGA. A testbench in VHDL finished up being useful to validate the correctness for the design. The VHDL that is put together rule been synthesized into gate level. Area and optimization that is timing done to quickly attain a tremendously low gate count of 436 while increasing the design rate to 178MHz Mentor Graphics and Xilinx ISE 6, electronic design automation (EDA) tool used.
* Mentor Graphics ModelSim simulation tool