VLSI Design Flow :

There are many standard tools available in market by various tool vendors for electronic

design automation. Figure below shows the complete VLSI design flow for the PLD design


The different steps involved in VLSI design flow are as follows,

Creating a project

Design entry

Functional simulation


Assigning the circuit inputs and outputs to specific pins of the PLD


Simulating the designed circuit for area and time constraints

Programming and configuring the design on chip.

VLSI design flow

1) Design Entry :

Design entry is the first step in the design of any VLSI circuit using EDA tools. In this

step the intended design is entered on the personal computer. Figure below shows the various

ways of design entry. The various ways in design entry are as follows,

Schematic entry

Design entry using Hardware Description Languages(HDL)

Using Finite State Machines (FSM)

EDIF entry

Ways of design entry

Schematic entry :

Schematic is the design developed by the digital designer using different logical gates

and digital ICs. The schematics can be drawn on the monitor screen by using the CAD tools. In

this entry the designer first designs the equivalent digital systems using K-Map and instead of

implementing the design on the breadboard the design can be tested using the simulators.

Hardware description languages :

Hardware description languages originally developed for circuit modelling. Now a days

these are used for complex hardware design. In this the design is represented in the form of

coding template by using the syntaxes of the HDL. The different HDLs used in practice are :




Finite state machines :

The design can be entered using the state diagrams of the sequential circuits. The CAD

tool can be used to draw the complete state diagram on the personal computer and simulated

for the required results. Now a days the EDA tools are available which will convert the

complete state diagram into the HDL code and this HDL code is further processed.

EDIF entry :

EDIF is the Electronic Data Interchange Format, an industry standard file format for

specifying a design net list. It is generated by a EDIF design-entry tool.

Input files : VHDL file (.vhd, .vhdl), Verilog file (.v), ABEL file (.abl, .abv), EDIF file

(.edf), Schematic file (.sch), State diagram file (.dia), User constraints file (.ucf). Or as

user generated in particular entry editor

Output files : VHDL file (.vhd, .vhdl), Verilog file (.v), ABEL file (.abl, .abv), EDIF

file (.edf), Schematic file (.sch), State diagram file (.dia, .asf), User constraints file


2) Functional/ Gate Level Simulation :

The functional gate level simulations are carried out to test the designs entered in the

design entry tools. The designs are tested by applying the test inputs are outputs are checked as

per the specifications. The important role of this simulations is to find the errors in the design

before the design is implemented in the target device (CPLD/FPGA). These simulations are

mainly carried out initial stages of the system design.

3) Compilers and Synthesis Tools :

A typical CAD software package contains several components. Analyze is the first step in the

synthesis flow. In this stage, the HDL code is checked for syntax errors. The Logic

optimization is the process that decreases the area or increases the speed of a design.

Normally the system designer develops the HDL code and the synthesis tool identifies

the syntax errors. Figure below shows the synthesis process. The synthesis process also

creates the netlist. Netlist is the description of the circuit developed by the HDL code.

Netlist is basically contains the connectors, instances and the connected signals.

Synthesis process

4) Assigning Constraint :

Design constraint is a subset of the values of a type. The set of possible values for an

object of a given type that can be subjected to a condition is called a constraint. The file

containing the information about the pins, there direction and locked pin of the selected

hardware device is called as User Constraints File (UCF). Before implementing the

design on the actual device this file is required which selects the particular functional

block (for CPLD) and configurrable logic block (for FPGA) on which design to be


5) Implementation :

In this step the design is implemented on the device. A library containing the design unit

in which a given component is declared is called as Target cell library. The target library is

used to determine the visible entity declaration under certain circumstances for a default

binding indication. The different steps in implementation are as follows,

Netlist translation :

A program that converts all input results into a single merged file.

Mapping or fitting :

Mapping is the step in which the logic elements are mapped to the logic functions on a

FPGA device. Fitting is the step to put the design logic into macrocell locations of the


Floor planning :

Floor planning step is to plan the logic in a design. In this step manually blocks of logic

in an FPGA are placed.

Place and route :

Placing is the process of assigning physical device cell locations to the logic in a design.

Routing is the process of assigning logical nets to physical wire segments in the FPGA

that interconnects logic cells.

Timing simulation :

This simulation step is carried out after the synthesis, placing and routing of the design.

The important role of this step is to check the dynamic timing details of the HDL code.

A timing analysis or a point-to- point delay analysis of a design network is called as

Static Timing Analysis.

6) Programming:

The final step of the design process is the downloading of the design on the device. In

this step a bit stream file is created, a bit stream is a stream of data that contains location

information for logic on a device, that is, the placement of Configurable Logic Blocks. This bit

stream file is downloaded on the device using programming. Programming is the process of

configuring the programmable interconnect in the FPGA or CPLD.