The counter counts from 0 to 9 for the up sequence, and 9 down to 0 for the down sequence. For the up sequence, the count and up signals must be '1' when count is '1' and up is '0' then counter starts count in downwards. If load signal becomes '1' then input data appears at output Q.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bcd_digit is
port (clk, reset: in std_logic;
cnt, up, load: in std_logic;
cbout: out std_logic;
d: in std_logic_vector (3 downto 0);
q: out std_logic_vector (3 downto 0));
end bcd_digit;
architecture bcd_digit_arch of bcd_digit is
signal reg: std_logic_vector (3 downto 0);
begin
process
begin
wait until clk = '1';
if reset = '1' then
reg <= x"0";
elsif load = '1' then
reg <= d;
elsif cnt = '1' and up = '1' then
if reg = x"9" then
reg <= x"0";
else
reg <= reg + x"1";
end if;
elsif cnt = '1' and up = '0' then
if reg = x"0" then
reg <= x"9";
else
reg <= reg - x"1";
end if;
end if;
end process;
q <= reg;
cbout <= '1'
when (cnt = '1' and up = '1' and reg = x"9")
or (cnt = '1' and up = '0' and reg = x"0")
else '0';
end bcd_digit_arch;