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CMOS Processing Technology
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Ac dc power converters
single phase full wave controlled rectifier
single phase half wave controlled rectifier
three phase full wave controlled rectifier
three phase half controlled rectifier
Amplifier
instrumentation amplifier
inverting amplifier
isolation amplifier
non inverting amplifier
operational amplifier
unity gain buffer
Analog integrated circuits
current to voltage converter
data converters
*
binary weighted resistor dac
*
counter type adc
*
dual slope type adc
*
flash type adc
*
r 2r ladder dac
*
successive approximation type adc
multivibrators
*
asymmetrical square wave generator
*
bistable multivibrators
*
monostable multivibrator
*
sawtooth waveform generator
*
triangular waveform generator
ocillators
op amp adder
op amp comparators
*
comparator as a duty cycle controller
*
comparator as a function generator
*
comparator ic lm 311
*
inverting comparator
*
non inverting comparator
*
voltage controlled oscillator
*
window comparator
opampdifferentiator
*
practical differentiator
*
summing differentiator
op amp integrator
*
difference integral
*
non inverting integrator
*
practical integrator
*
summing integrator
peak detector
phase locked loop
*
pll applications
*
pll ic 565
precision rectifier
*
modified precision full wave rectifier
*
non saturated type precision half wave rectifier
*
precision full wave rectifier
*
saturating type precision hwr
sample hold circuit
schmitt trigger
*
asymmetrical inverting schmitt trigger
*
inverting schmitt trigger
*
non inverting schmitt trigger
subtractordifference amplifier
voltage regulator
*
adjustable negative voltage regulator ics
*
current booster
*
dual power supply
*
low drop out voltage regulators
*
series regulator using op amp
*
three terminal adjustable voltage regulator ics
*
three terminal fixed voltage regulator ics
*
voltage regulators ics
Analog CMOS Design
CMOS Differential Amplifier
CMRR
Current Mirrors
Differential Amplifier
Cascode Op amp
Folded Cascode Op amp
Two Stage Op amp
MOSFET Amplifiers
Cascode Amplifier
CMOS Inverter as an Amplifier
Common Drain Amplifier
Common Gate Amplifier
Common Source Amplifier
CS Amplifier with Active Load
CS Amplifier with Current Source Load
Current Source Load Inverter
Frequency Response of CS Amplifier
PMOS Load Inverter
Push Pull Inverter
Body Effect
Current Sinks
Current Source
C V Characteristics
Enhancement MOSFET Physical Structure
I V Characteristics of PMOS Transistor
Linear Region of Operation
MOSFET Small Signal Model
Saturation Region of Operation
Threshold Voltage
MOSFET Parasitics
Interconnect Capacitance
Interconnect Delay Model
Interconnect Resistance
Parasitic capacitance Models
Parasitic Capacitances
Parasitic Capacitances MOSFETS
Source Drain Resistance
RF CMOS Circuits
Low Noise Amplifier
Mixers
Oscillator
RF Circuits
ADC Circuits
ADC DAC Blocks
DAC Circuits
Sampling Analog Signals
Signal Conditioning
Signal Quantization
Combinational logic circuits
arithmetic logic unit
binaryaddersubtractor
boolean algebra
decoders
demultiplexers
encoders
full adder
full subtractor
half adder
half subtractor
multiplexer
Control systems
feedback control system
transfer function and characteristic equation
transfer function of electrical circuit
Dccircuits
energy sources
kirchhoffs current law
kirchhoffs voltage law
maximum power transfer theorem
mesh analysis
nodal analysis
nortons theorem
source transformations
superposition theorem
thevenins theorem
Dc dc converter chopper
classification of chopper
step down chopper
step up chopper
switched mode power supplies smps
uninterruptible power supply ups
Dc to ac inverter
half bridge dc ac inverter
single phase full bridge inverter
single pwm inverters
three phase inverter
Digital CMOS Design
CMOS Inverter
Beta Ratio Effects
Dissipation due to Direct Path Currents
Dynamic Power Consumption
Noise Margin
Power Delay Product in CMOS
Power Dissipation minimization Techniques
Static Power Consumption
VTC CMOS Inverter
Width Length Ratio Calculation of CMOS
CMOS Layout Design
CMOS Design Flow
CMOS lambda Design Rules
Design Rule Check
Inverter Layout
Lambda based design rules
Layout Design Rules
Layout of logic gates
Micron Design Rules
Stick Diagrams
Technology scaling
Types of Scaling
CMOS Logic Gates
CMOS 4 input NOR gate
CMOS AND gate
CMOS Compound Gates
CMOS Half adder
CMOS NAND Gate
CMOS NOR Gate
CMOS OR gate
CMOS XNOR and XOR
Pull up and Pull Down Networks
Rules for Designing Complementary CMOS Gates
Three input CMOS NAND gate
MOS Capacitor
Band Diagram of Ideal MOS
Band Diagram of Nonideal MOS
Band Diagram of Nonideal MOS with Bias
MOS Definitions
MOSFET Fundamentals
MOSFET Fundamentals Introduction
Basic MOS Transistors
MOSFET as Switch
n channel Depletion Mode MOSFET
n channel Enhancement Mode MOSFET
p channel Depletion Mode MOSFET
p channel Enhancement Mode MOSFET
Non Ideal Effects
Body Effect
Hot Electron Effect
Mobility Variation
Subthreshold Conduction
Velocity Saturation
Pass Transistor Logic
2 1 MUX using transmission gate
4 1 multiplexer using CMOS logic
OR gate using pass transistor logic
Transmission Gate
XNOR gate using pass transistor logic
XOR gate using pass transistor logic
Propagation Delay
Delay Estimation
Elmore Delay Model
Parasitic Capacitances
RC Delay Model of Inverter
RC Delay Model of NAND Gate
Digital logic families
cmos and ttl interfaces
cmos logic
noise margin
ttl logic
Digital logic gates
and gate
nand gate
nor gate
not gate
or gate
xnor gate
xor gate
Electronic components
capacitors
*
ac analysis of capacitor
*
capacitive reactance
*
capacitorbasics
*
capacitor charge equations
*
capacitor types
*
capacitors in parallel combination
*
capacitors in series combination
*
colour coding in capacitors
*
multiple plate capacitor
*
parallel plate capacitor
inductors
*
inductive reactance
*
inductor basics
*
inductors in parallel combination
*
inductors in series combination
*
mutual inductance
*
self inductance
resistors
transformers
Electronic devices
diode
insulated gate bipolar transistor
mosfet
power mosfet
transistors
Electronic instruments
digital voltmeters
*
dual slope dvm
*
ramp type dvm
oscilloscope
*
cathode ray oscilloscope
waveform
Electronic systems
brushless dc motors
induction motor
public address system
separately excited dc motor
servomotors
stepper motor
Finite state machines
Algorithmic State Machines
*
ASM chart 2 bit up down counter
*
ASM chart for signal generator
*
ASM charts
*
ASM Chart Tool for Sequential Circuit Design
*
Design with Multiplexers
Asyncronous FSM Design
*
Analysis of Asynchronous Sequential Machines
*
Asynchronous FSM
*
Design of Asynchronous Sequential Machine
*
Design Procedure for Asynchronous Sequential Circuits
*
Essential Hazards
*
Hazardfree circuit
*
Modes of Asynchronous Sequential Machines
FSM Applications
*
UART Transmitter Design
*
UART Receiver Design
*
Traffic Light Controller
*
Simple Traffic Controller
*
Serial Adder
*
Sequential Counters JKFF
*
Sequential Counters DFF
*
Sequential Counters
*
Sequence Generator
*
Sequence Detector
*
Lift Controller
Hazards
*
Detection of Static Hazards
*
Dynamic Hazards
*
Effects of Hazards
*
Elimination of Static Hazards
*
Static Hazards
Metastability
*
JK flipflop State Machine
*
Metastability measurement setup
*
Metastability Synchronizer
State Machine Fundamentals
*
Analysis of Sequential Circuits
*
Excitation Tables for Flip Flops
*
Finite State Machine Diagram
*
Mealy Finite State Machine
*
Moore Finite State Machine
*
Need for State Machines
*
State Diagrams
*
State Encoding Techniques
*
State Machine
*
State Minimization
*
VHDL Coding of FSM
Number systems
binary number system
binarynumbers
binary to decimal conversion
decimal number system
decimal to binary conversion
decimal to hexadecimal conversion
decimal to octal conversion
hexadecimal number system
hexadecimal to decimal conversion
octal number system
octal to decimal conversion
Programmable Logic Device Architectures
CPLD
Advanced Micro Devices AMD CPLDs
Altera FLASH logic CPLDs
Altera MAX 7000 CPLD
Complex Programmable Logic Device CPLDs
CPLD Packaging
Cypress FLASH370 CPLDs
ICT PEEL Arrays
Lattice CPLDs
XC9500 CPLD Family
FPGA
Field programmable gate array FPGA
FPGA Programming
FPGA Structures
XC4000 FPGA Family
XC5200 FPGA Family
Programmable Logic Devices
Application Specific Integrated Circuits ASIC
Discrete Devices Technology
Evolution of Programmable Logic Devices
Programmable Array Logic PAL
Programmable Logic Array PLA
Programmable Logic Device Technology
Programmable Read only Memory PROM
Simple Programmable Logic Devices SPLD
Programmable logic devices
complex programmable logic device
field programmable gate array
generic array logic
programmable array logic
programmable logic array
programmable roms
Sequential logic circuits
asynchronous counter
counters
d flip flop to jk flip flop
d flip flop to sr flip flop
d flip flop
flip flop excitation table
jk flip flop to d flip flop
jk flip flop to sr flip flop conversion
jk flip flop to t flip flop
jk flip flop
parallel in to parallel out pipo shift register
parallel in to serial out piso shift register
serial in to parallel out sipo shift register
serial in to serial out siso shift register
shift registers
sr flip flop to d flip flop
sr flip flop to jk flip flop conversion
sr flip flop
synchronous counter
toggle flip flop
System On Chip
Clock Distribution
Clock Jitter
Clock Skew
Interconnects
Interconnect Routing Techniques
RC Wire Model
Wire Capacitance
Wire Resistance
Wiring Parasitics
Power Distribution
Power Distribution Techniques
Power Optimization
Signal Integrity Issues
Supply and Ground Bounce
SOC Designs
Design Validation
EMI Immune Design
IO Architectures and Pad Design
Off Chip Connections
One Phase System
Two Phase System
Thyristor
characteristics of thyristor
gate characteristics of thyristor
ratings of thyristor
thyristor commutation
thyristor commutation techniques
triggering circuit of thyristor
VHDL
*
Hardware Description Languages
*
Introduction to VHDL
*
VHDL Program Format
*
Structure of VHDL Program
*
Data Flow Modeling
*
Behavioral modeling
*
Data types
*
Structural modeling
*
Mixed modeling
*
Data Objects and Identifiers
*
Hardware Description Languages
*
Operators
*
Synthesis
*
Types of Delays
*
VHDL Program Format
*
VHDL Simulation
*
VHDL statements
*
Attributes
*
Configuration Declaration
*
Configuration Specification
*
Configurations
*
Function
*
Generics
*
Package
*
Procedure
*
Subprograms
*
TestBench
*
Adder Subtractor
*
ALU
*
Carry ripple adder
*
Comparators
*
Divider
*
Full adder
*
Half adder
*
Multiplier
*
n bit adder
*
Simple Equality Comparator
*
Subtractor
*
Assertion statement
*
Block Statement
*
Component Declarations
*
Component Instantiation
*
Concurrent Signal Assignments
*
Exit Statements
*
For generate Statement
*
Generate Statements
*
Loop statements
*
Next statements
*
Report Statement
*
Return statements
*
Wait Statements
*
When Statement
*
with Select Statement
Vlsi
Evolution of Digital IC Technologies
IC Development Cycle
VLSI Technology
VLSI Design Flow
CMOS IC Technology
*
Boundary Scan Standards
*
Boundary Scan
*
Built in Logic Block Observer BILBO
*
Built in Self Testing BIST
*
Combinational Logic Testing
*
Controllability
*
Fault Coverage
*
Fault Modeling
*
Full Scan
*
IC Testing
*
JTAG TAP Controller
*
JTAG
*
Linear Feedback Shift Register LFSR
*
Need of Design for Testability
*
Observability
*
Partial Scan
*
Scan Path Testing
*
Signature Analysis
*
Stuck open and Stuck short Faults
*
Proj 1 Modulator for digital terrestrial television according to the DTMB standard
*
Proj 2 CAN Controller Design
*
Proj 3 Router Architecture for Junction Based Source Routing
*
Proj 4 Design Space Exploration Of Field Programmable Counter
*
Proj 5 Mobile Broadband Receiver
*
Proj 6 OBJECT TRACKING ALGORITHM
*
Proj 7 Hardware Software Runtime Environment for Reconfigurable Computers
*
Proj 8 Face Detection System Using Haar Classifiers
*
Proj 9 Fast Hardware Design Space Exploration
*
Proj 10 Speeding Up Fault Injection Campaigns on Safety Critical Circuits
*
Proj 11 HIGH SPEED 4 BIT SFQ MULTIPLIER
*
Proj 12 Universal Cryptography Processorfor Smart Cards
*
Proj 13 HIGH SPEED MULTIPLIER USING SPURIOUS POWER SUPPRESSION
*
Proj 14 LOSSLESS DATA COMPRESSION HARDWARE ARCHITECTURE
*
Proj 15 VLSI Architecture For Removal Of Impulse Noise In Image
*
Proj 16 PROCESSOR ARCHITECTURES FOR MULTIMEDIA
*
Proj 17 High Speed Multiplier Accumulator Using SPST
*
Proj 18 Power Efficient Logic Circuit Design
*
Proj 19 Data Transfer for AMBA Bus
*
Proj 20 ATM Knockout Switch Concentrator
*
Proj 21 Synthesis of Asynchronous Circuits
*
Proj 22 AMBA AHB compliant Memory Controller
*
Proj 23 Ripple Carry and Carry Skip Adders
*
Proj 24 32bit Floating Point Arithmetic Unit
*
Proj 25 CRC Circuit Architecture
*
Proj 26 ON CHIP PERMUTATION NETWORK FOR MULTIPROCESSOR
*
Proj 27 VLSI Systolic Array Multiplier for signal processing Applications
*
Proj 28 Floating point Arithmetic Logic Unit
*
Proj 29 DDR SDRAM CONTROLLER
*
Proj 30 FFT Processor Using Radix 4 Algorithm
*
Proj 31 bit RISC Processor
*
Proj 32 SMART SENSOR
*
Proj 33 Fuzzy based PID Controller
*
Proj 34 Stepper Motor Controller
*
Proj 35 I2C Bus Controller
*
Proj 36 Solar Power Saving System for Street Lights and Automatic Traffic Controller
*
Proj 37 Fuzzy Based Mobile Robot Controller
*
Proj 38 Realtime Traffic Light Control System
*
Proj 39 Digital Space Vector PWM Three Phase Voltage Source Inverter
*
Proj 40 Complex Multiplier Using Advance Algorithm
*
Proj 41 Discrete Wavelet Transform (DWT) for Image Compression
*
Proj 42 Gabor Filter for Fingerprint Recognition
*
Proj 43 Floating Point Fused Add Subtract and multiplier Units
*
Proj 44 ORTHOGONAL CODE CONVOLUTION CAPABILITIES
*
Proj 45 Flip Flops for High Performance VLSI Applications
*
Proj 46 Low Power Video Compression Achitecture
*
Proj 47 Power Gating Implementation with Body Tied Triple Well Structure
*
Proj 48 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
*
Proj 49 LOW POWER MULTIPLIER USING COMPOUND CONSTANT DELAY LOGIC
*
Proj 50 Flash ADC using Comparator Scheme
*
Proj 51 High Speed Floating Point Addition and Subtraction
*
Proj 52 LFSR based Pseudorandom Pattern Generator for MEMS
*
Proj 53 Power Optimization of LFSR for Low Power BIST
*
Proj 54 VENDING MACHINE USING VERILOG
*
Proj 55 VLSI ARCHITECTURES FOR DWT
*
Proj 56 Cache Memory Controller
*
Proj 57 Chip For Prepaid Electricity Billing
*
Proj 58 High Speed Network Devices Using Reconfigurable Content Addressable Memory
*
Proj 59 Bit Carry Look Ahead Adder
*
Proj 60 256 bit Parallel Prefix Adders
*
Proj 61 Mutual Authentication Protocol
*
Proj 62 Overlap based Logic cell
*
Proj 63 Low Power Adder Compressors
*
Proj 64 UTMI AND PROTOCOL LAYER FOR USB2.0
*
Proj 65 5 stage Pipelined Architecture of 8 Bit Pico Processor
*
Proj 66 Controller Design for Remote Sensing Systems
*
Proj 67 Test Pattern Generation for BIST
*
Proj 68 Faster Dadda Multiplier
*
Proj 69 SINGLE CYCLE ACCESS STRUCTURE FOR LOGIC TEST
*
Proj 70 Low Drop Out Voltage Regulator
Vlsi design for testability
Boundary Scan Standards
Boundary Scan
Built in Logic Block Observer BILBO
Built in Self Testing BIST
Combinational Logic Testing
Controllability
Fault Coverage
Fault Modeling
Full Scan
IC Testing
JTAG TAP Controller
JTAG
Linear Feedback Shift Register LFSR
Need of Design for Testability
Observability
Partial Scan
Scan Path Testing
Signature Analysis
Stuck open and Stuck short Faults
Mini projects
2 Bit Parallel or Flash Analog to Digital Converter
3 Bit Flash Type Analog to Digital Converter
3 BIT PARALLEL to SERIAL DATA CONVERTER
4 1 MULTIPLEXER
4 Bit Binary Counter
AMPLITUDE MODULATION AND DEMODULATION
AMPLITUDE MODULATION AND DEMODULTION USING BJT AMPLIFIER AND DIODE DETECTOR
ANALOG SIGNAL DIVIDER
Analog Signals Multiplier
ANALOG TRNSMITTER AND RECEIVER
ASK Modulation using OPAMP
A statistical comparison of binary weighted and R 2R 4 Bit DAC
Asynchronous Device for Serial Data Transmission and Reception for android data transmission
Asynchronous Modulo 16 Down Counter
Audio Amplifier circuit with noise filtering
AUTOMATIC RESISTANCE METER FOR 3 PHASE INDUCTION MOTOR DESIGN AND SIMULATION
Bistable Multivibrator using Asymmetrical Mosfet Triggering
CMOS Based Analog Function Generator
COMPANDER
COMPANDING CIRCUIT USING OPAMPS
DC boost circuit using 555 timer
DECADE COUNTER
Decoder and its Analysis
Design and Modelling of Notch Filter using Universal Filter FLT U2
Design and Phase Frequency Detector Using Different Logic Gates in CMOS Process Technology
Design of Astable Multivibrator Circuit
DESIGN OF OP AMP USING CMOS WITH IMPROVED PARAMETERS
DESIGN OF VARIABLE FREQUENCY
Digital Thermometer using 1N4148 Diode
DIGITAL TO ANALOG CONVERTER USING 8 BIT WEIGHTED RESISTORS
FM TRANSMITTER
Four bit Arithmetic Logical Unit
FREQUENCY SHIFT KEYING USING 555
Function Generator Using Op Amps
Generation of PWM using 555 timer IC
HARTLEY AND COLPITTS OSCILLATOR USING OPAMP
Heart Beat sensor using Photoplethysmography
IC 555 timer as an Audio Amplifier
LOW COST MOSFET BASED MOTOR DRIVER
Mono stable multivibrator
MOSFET BASED MOTOR DRIVER
MOSFET driver circuit to interface MOSFETs with microcontroller for high speed application
PAM MODULATION AND DEMODULATION
Phase Locked Loop
PIR MOTION SENSOR
PULSE WIDTH MODULATION
PULSE WIDTH MODULATION AND DEMODULATION
Regulated DC Power Supply using Series Voltage Regulator
SCHMITT TRIGGER USING 555
Serial To Parallel Convertor
Short Circuit Protected Power Supply
Short Range radio Transmitter and Receiver
SIMULATION OF FUNCTION GENERATOR
Small Range Digital Thermometer using 1N4148
Three Phase Inverter using MOSFET to drive BLDC motor and general three phase Load
THREE STAGE AMPLIFIER WITH CURRENT LIMITER
TRANSISTOR TESTER USING IC 555 TIMER
Truly random and Pseudorandom Data Generation with Thermal Noise
UNIVERSAL ACTIVE FILTER
VOLTAGE REGULATOR
Zener Diode Tester
ZENER DIODE TESTER USING 555 TIMER
Zero Crossing Detector
VOLTAGE REGULATOR
ZENER DIODE TESTER USING 555 TIMER
Zero Crossing Detector
Vlsi projects
Proj 1 Modulator for digital terrestrial television according to the DTMB standard
Proj 2 CAN Controller Design
Proj 3 Router Architecture for Junction Based Source Routing
Proj 4 Design Space Exploration Of Field Programmable Counter
Proj 5 Mobile Broadband Receiver
Proj 6 OBJECT TRACKING ALGORITHM
Proj 7 Hardware Software Runtime Environment for Reconfigurable Computers
Proj 8 Face Detection System Using Haar Classifiers
Proj 9 Fast Hardware Design Space Exploration
Proj 10 Speeding Up Fault Injection Campaigns on Safety Critical Circuits
Proj 11 HIGH SPEED 4 BIT SFQ MULTIPLIER
Proj 12 Universal Cryptography Processorfor Smart Cards
Proj 13 HIGH SPEED MULTIPLIER USING SPURIOUS POWER SUPPRESSION
Proj 14 LOSSLESS DATA COMPRESSION HARDWARE ARCHITECTURE
Proj 15 VLSI Architecture For Removal Of Impulse Noise In Image
Proj 16 PROCESSOR ARCHITECTURES FOR MULTIMEDIA
Proj 17 High Speed Multiplier Accumulator Using SPST
Proj 18 Power Efficient Logic Circuit Design
Proj 19 Data Transfer for AMBA Bus
Proj 20 ATM Knockout Switch Concentrator
Proj 21 Synthesis of Asynchronous Circuits
Proj 22 AMBA AHB compliant Memory Controller
Proj 23 Ripple Carry and Carry Skip Adders
Proj 24 32bit Floating Point Arithmetic Unit
Proj 25 CRC Circuit Architecture
Proj 26 ON CHIP PERMUTATION NETWORK FOR MULTIPROCESSOR
Proj 27 VLSI Systolic Array Multiplier for signal processing Applications
Proj 28 Floating point Arithmetic Logic Unit
Proj 29 DDR SDRAM CONTROLLER
Proj 30 FFT Processor Using Radix 4 Algorithm
Proj 31 bit RISC Processor
Proj 32 SMART SENSOR
Proj 33 Fuzzy based PID Controller
Proj 34 Stepper Motor Controller
Proj 35 I2C Bus Controller
Proj 36 Solar Power Saving System for Street Lights and Automatic Traffic Controller
Proj 37 Fuzzy Based Mobile Robot Controller
Proj 38 Realtime Traffic Light Control System
Proj 39 Digital Space Vector PWM Three Phase Voltage Source Inverter
Proj 40 Complex Multiplier Using Advance Algorithm
Proj 41 Discrete Wavelet Transform (DWT) for Image Compression
Proj 42 Gabor Filter for Fingerprint Recognition
Proj 43 Floating Point Fused Add Subtract and multiplier Units
Proj 44 ORTHOGONAL CODE CONVOLUTION CAPABILITIES
Proj 45 Flip Flops for High Performance VLSI Applications
Proj 46 Low Power Video Compression Achitecture
Proj 47 Power Gating Implementation with Body Tied Triple Well Structure
Proj 48 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
Proj 49 LOW POWER MULTIPLIER USING COMPOUND CONSTANT DELAY LOGIC
Proj 50 Flash ADC using Comparator Scheme
Proj 51 High Speed Floating Point Addition and Subtraction
Proj 52 LFSR based Pseudorandom Pattern Generator for MEMS
Proj 53 Power Optimization of LFSR for Low Power BIST
Proj 54 VENDING MACHINE USING VERILOG
Proj 55 VLSI ARCHITECTURES FOR DWT
Proj 56 Cache Memory Controller
Proj 57 Chip For Prepaid Electricity Billing
Proj 58 High Speed Network Devices Using Reconfigurable Content Addressable Memory
Proj 59 Bit Carry Look Ahead Adder
Proj 60 256 bit Parallel Prefix Adders
Proj 61 Mutual Authentication Protocol
Proj 62 Overlap based Logic cell
Proj 63 Low Power Adder Compressors
Proj 64 UTMI AND PROTOCOL LAYER FOR USB2.0
Proj 65 5 stage Pipelined Architecture of 8 Bit Pico Processor
Proj 66 Controller Design for Remote Sensing Systems
Proj 67 Test Pattern Generation for BIST
Proj 68 Faster Dadda Multiplier
Proj 69 SINGLE CYCLE ACCESS STRUCTURE FOR LOGIC TEST
Proj 70 Low Drop Out Voltage Regulator
Matlab projects
Proj 1 DESIGN OF FIR FILTER USING SYMMETRIC STRUCTURE
Proj 2 Hybrid Median Filter design
Proj 3 Designing an Optimal Fuzzy Logic Controller of a DC Motor
Proj 4 Brain Tumour Extraction from MRI Images
Proj 5 Mammogram of Breast Cancer detection
Proj 6 VEHICLE NUMBER PLATE RECOGNITION USING MATLAB
Proj 7 High Speed Rail Road Transport Automation
Proj 8 ECONOMIC AND EMISSION DISPATCH USING ALGORITHMS
Proj 9 DC DC Converters for Renewable Energy Systems
Proj 10 ADAPTIVE FILTERING USED IN HEARING AIDS OF IMPAIRED PEOPLE
Proj 11 MODELING OF TEMPERATURE PROCESS USING GENETIC
Proj 12 CDMA MODEM DESIGN USING DIRECT SEQUENCE SPREAD SPECTRUM (DSSS)
Proj 13 Hydropower Plant Models
Proj 14 IEEE 802.11 Bluetooth Interference Simulation study
Proj 15 Inverse Data Hiding in a Classical Image
Proj 16 JPEG COMPRESSOR
Proj 17 Digital Image Arnold Transformation and RC4 Algorithms
Proj 18 Hand Gesture Recognition
Proj 19 Performance Study for Hybrid Electric Vehicles
Proj 20 Wi Fi Access Point Placement For Indoor Localization
Proj 21 Neural Network Based Face Recognition
Proj 22 Tree Based Tag Collision Resolution Algorithms
Proj 23 Back Propagation Neural Network for Automatic Speech Recognition
Proj 24 Orthogonal Frequency Division Multiplexing(OFDM) Signaling
Proj 25 Smart Antenna Array Using Adaptive Beam forming
Proj 26 Implementation of Butterworth Chebyshev I and Elliptic Filter for Speech Analysis
Proj 27 Simulator for Autonomous Mobile Robots
Proj 28 Method to Extract Roads from Satellite Images
Proj 29 Remote Data Acquisition Using Cdma RfLink
Proj 30 AUTOMATIC TRAIN OPERATION AND CONTROL
Proj 31 Detection of Objects in Crowded Environments
Proj 32 Armature Controlled Direct Current
Proj 33 Distribution Transformer For
Proj 34 WAVELET TRANSFORM AND S TRANSFORM BASED ARTIFICIAL NEURAL
Proj 35 MULTISCALE EDGE BASED TEXT EXTRACTION
Proj 36 Transient Stability Analysis of Power System
Proj 37 Single phase SPWM Unipolar inverter
Proj 38 Induction Generator for Variable Speed Wind Energy Conversion Systems
Proj 39 Extra High Voltage Long Transmission Lines
Proj 40 FAULT ANALYSIS IN HVDC
Proj 41 Realtime Control of a Mobile Robot
Proj 42 Reactive Power Compensation in Railways
Proj 43 POWER UPGRADATION IN COMPOSITE AC DC TRANSMISSION SYSTEM
Proj 44 Dynamic Analysis of Three Phase Induction Motor
Proj 45 Fuzzy Controlled SVC for Transmission Line
Lab test and measurement
Antenna and Wave Propagation
Exp 1
Exp 2
Exp 3
Exp 4
Exp 5
Exp 6
Exp 7
Exp 8
Exp 9
Exp 10
Exp 11
Exp 12
Exp 13
Exp 14
Circuit simulation and Tools
exp 1
exp 2
exp 3
exp 4
exp 5
exp 6
exp 7
exp 8
exp 9
exp 1
exp 2
exp 3
exp 4
exp 5
exp 6
exp 7
exp 8
Exp 1 SSDC
Exp 2 SSDC
Exp 3 SSDC
Exp 4 SSDC
Exp 5 SSDC
Exp 6 SSDC
Exp 7 SSDC
Exp 8 SSDC
Exp 9 SSDC
Quiz
index
Question Answer Analog Integrated Circuits Main
Question Answer Digital Logic circuits Main
Question Answer DC circuits Main
Question Answer DC circuit analysis Main
Question Answer Analog Communication Main
Question Answer Computer Organization Main
Project ideas
Arduino projects
arduino projects