Home > VHDL > Arithmetic Circuits > n bit adder
Structural implementation of the N-bit adder :
```library IEEE;
use IEEE.std_logic_1164.all;

generic(N : integer := 16);                             -- The width of the adder is determined by generic N
port (a : in std_logic_vector(N downto 1);
b : in std_logic_vector(N downto 1);
cin : in std_logic;
sum : out std_logic_vector(N downto 1);
cout : out std_logic);

port (a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
cout : out std_logic);
end component;
signal carry : std_logic_vector(0 to N);
begin
carry(0) <= cin;
cout <= carry(N);
-- instantiate a single-bit adder N times
gen: for I in 1 to N generate
add: adder port map(a => a(I), b => b(I), cin => carry(I - 1), sum => sum(I), cout => carry(I));
end generate;
end structural;

```
Behavioral implementation of the N-bit adder :
```library IEEE;
use IEEE.std_logic_1164.all;

generic(N : integer := 16);                 -- The width of the adder is determined by generic N
port (a : in std_logic_vector(N downto 1);
b : in std_logic_vector(N downto 1);
cin : in std_logic;
sum : out std_logic_vector(N downto 1);
cout : out std_logic);

begin
p1: process(a, b, cin)
variable vsum : std_logic_vector(N downto 1);
variable carry : std_logic;
begin
carry := cin;
for i in 1 to N loop
vsum(i) := (a(i) xor b(i)) xor carry;
carry := (a(i) and b(i)) or (carry and (a(i) or b(i)));
end loop;
sum <= vsum;
cout <= carry;
end process p1;
end behavioral;
```