Project Title: 256-bitParallel Prefix Adders
Parallel prefix adder is considered the most trusted and versatile for binary addition. Parallel Prefix adders are best suited to VLSI execution. Quantities of synchronous prefix adder structures have already been proposed over time being past to Optimize area, fan-out, logic depth and inter connect count. This project presents a approach that is brand name redesign that is new basic operators found in parallel prefix architectures. The amount of multiplexers present each little bit of a FPGA is considered right here for the redesign for the operators being fundamental in synchronous prefix tree. This design that is new implemented with 128-bit width operands of numerous prefix that is parallel on Xilinx Spartan FPGA. The outcome which are experimental that The approach that is completely new of operators make some for the parallel prefix adder's architectures faster and area effective.