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Project Title: Flash ADC using Comparator Scheme

Brief Introduction:

Analog to Digital converter (ADC) are the unit that is most that is very important convert analog information to corresponding electronic kinds. ADC are generally found in the applying kind section of smart phones, cameras, electronic TVs etc. Flash and pipeline ADCs are usually useful for high speed application. The flash type may be the faster of this two, perhaps not benefited to the greater quality because it raise the no. of component and therefore eat up more energy. Numerous flash architecture that is ADCs are described in the works that are literary. To improve the appearance of flash kind converter architecture that is a few been proposed such as two- period architecture. However the issue that is major these approach can it be makes use of analog component as well as because the technology is scaling right down analog component are tough to integrate and its particular performance will soon be degraded also. This ADC additionally require high gain comparators which can be differential more complex and resistor that is require to deliver reference voltage. Other drawback of the approach would be the lowering of throughput and linearity that is bad is differential. However the performance for the system that is improve that is electronic the technology is scaling. Presently easy and faster flash type converter are proposed concerning the Threshold Inverter Quantization method. This technique eradicate the usage of the resistor ladder and reduce the complexity associated with converter nevertheless it is process parameter dependent . This makes use of two Cascaded CMOS that is electronic inverter which behave that is first an analog voltage comparator along with the 2nd improve the voltage gain with this comparator. Guide voltage about the comparator is modification by varying the width concerning the transistor and maintaining the transistor size constant since it is more sensitive and painful and possesses a effect that is limit voltage that is significant. Another strategy is to use CMOS LTE being a comparator which boost the Power supply Rejection Ratio for the circuit. This system is process parameter dependent also. In this paper , we propose a Flash ADC which may be completely implemented only using cells that can be standard. This method helps increase the transformation rate that is high-speed. This permits the designer to stay in the mature design that is electronic and effortlessly lessen the potential risks and time-to-market.

Hardware Details:

  • 4 bit flash ADC
  • MUX based decoder

Software Details:

  • Tanner 13 tool

* standard digital CMOS technology

Block Diagram:

For more details