Power Dissipation minimization Techniques

Power Dissipation minimization Techniques :

• In order to minimize the power dissipation in digital integrated circuits three techniques are used. 1) Voltage Scaling 2) Clock Frequency Reduction and 3) Switched Capacitance Reduction. In voltage scaling the supply voltage is reduced.
• As the dynamic power dissipation and short circuit power dissipation are dependent on power supply voltage, reducing the power supply voltage reduces the power dissipation. In clock frequency reduction technique the clock frequency of the processors is reduced.
• Reducing clock frequency is not leads to efficient power reduction. But, since processors are having power down modes, the clock signal are not used in the modes which leads to reduction in power dissipation.
• In switched capacitance reduction, reducing the switched capacitance is helpful to reduce the clock frequency.

Total Power Consumption of CMOS Inverter :

Now, by considering all the power dissipation components i.e. dynamic power dissipation, power dissipation in direct current paths and static power dissipation, the total power dissipation is given by,

		Ptotal	=	Pdynamic + Pdp  + Pstatic		  
			=	CL VDD2 f + tdp * VDD * Ip * f + Ileakage VDD 
			=	(CLVDD2 +  tdp * VDD * IP) f + Ileakage VDD