Pull up and Pull Down Networks : A complementary MOS gate is a combination of two networks the Pull Up Network (PUN) and the Pull Down Network (PDN). Figure below shows the 'N' input logic gate where all inputs are distributed to both the PUN and PDN. The function of PUN is to provide a connection between VDD and Vout to pull Vout to logic '1' whereas the function of PDN is to provide connection between GND and Vout to pull Vout to logic '0'. The PUN and PDN are complementary to each other.

Normally the PDN is consisting of NMOS devices whereas PUN is consisting of PMOS devices.

The main reason for this combination is that NMOS transistors produce "strong zeros" and PMOS devices generate "strong ones". In order to explain this concept consider the PUN constructed using PMOS and NMOS transistors as shown in Figure. For PUN the output should be pulled to logic high (i.e. VDD). If we use NMOS transistor then the voltage level of F is VDD–VTn. Where VTn is threshold voltage of NMOS and if we use PMOS transistor then the voltage level of F is VDD. Thus PMOS produces strong '1' and NMOS produces weak '1'.

Consider the PDN constructed using PMOS and NMOS transistors as shown in

Figure. For PDN the output should be pulled to logic low (i.e. GND). If we use NMOS transistor then the voltage level of F is '0' V and if we use PMOS transistor then the voltage level of F is VTp i.e. Threshold voltage of PMOS. Thus NMOS produces strong '0' and PMOS produces weak '0'.

Difference between Pull up and Pull down Networks :