The pre-defined, synthesizable data
attributes in VHDL are,
data'LENGTH : Returns vector size.
data'RANGE : Returns vector range.
data'REVERSE_RANGE : Returns vector range in reverse order.
data'LOW : Returns lower array index.
data'HIGH : Returns upper array index.
data'LEFT : Returns leftmost array index.
data'RIGHT : Returns rightmost array index.
Signal Attributes :
Although the most signal attributes are used for simulation purposes only, the
first two in the list bellow are synthesizable.
tick'EVENT : Returns true when an event occurs.
tick'STABLE : Returns true if no event has occurred.
tick'LAST_ACTIVE : Returns the time elapsed.
tick'LAST_VALUE : Returns the value before the last event.
tick'ACTIVE : Returns true.
tick'QUIET
tick'LAST_EVENT : Returns the time elapsed since last event.
User-defined Attributes :
The attributes discussed in previous section are of the type HIGH, RANGE, EVENT, etc. and are called as pre-defined. However, VHDL also has the construction of user defined attributes. To have a user-defined attribute, it can declared and specified.
The syntax is the follows,
Attribute declaration :
ATTRIBUTE attribute_test: attribute_test;
Attribute specification :
ATTRIBUTE attribute_test OF target_test: class IS value;
where :
attribute_test any data type (BIT, INTEGER, STD_LOGIC_VECTOR)
class : TYPE, SIGNAL, FUNCTION
value: '0', 27, "00 11 10 01"