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Arithmetic Circuits
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VHDL Introduction
Hardware Description Languages
Introduction to VHDL
VHDL Program Format
Structure of VHDL Program
Data Flow Modeling
Behavioral modeling
Data types
Structural modeling
Mixed modeling
Data Objects and Identifiers
Hardware-Description-Languages
Operators
Synthesis
Types-of-Delays
VHDL-Program-Format
VHDL-Simulation
VHDL-statements
VHDL Adavanced
Attributes
Configuration-Declaration
Configuration-Specification
Configurations
Function
Generics
Package
Procedure
Subprograms
TestBench
VHDL Arithmetic-Circuits
Adder-Subtractor
ALU
Carry-ripple-adder
Comparators
Divider
Full-adder
Half-adder
Multiplier
n-bit-adder
Simple-Equality-Comparator
Subtractor
VHDL Concurrent-Statements
Assertion-statement
Block-Statement
Component-Declarations
Component-Instantiation
Concurrent-Signal-Assignments
Exit-Statements
For-generate-Statement
Generate-Statements
Loop-statements
Next-statements
Report-Statement
Return-statements
Wait-Statements
When-Statement
with-Select-Statement
Counters
Counters
8-bit-Loadable-Counter
BCD-Up-down-Counter
Binary-Down-Counter
Binary-up-counter
Binary-Up-Down-Counter
Counter-examples
Johnson-Counter
synchronous-asynchronous-counters
Two-digit-counter
Flipflops
Flipflops
DFF
D-latch
JKFF
TFF
Logic-Circuits
Logic-Circuits
3-6-Binary-Decoder
3-8-Binary-Decoder
4_1_Mux
4-1-Mux-using-Different Modeling-Styles
4-2-Priority-Encoders
8-3-Binary-Encoder
8-3-Binary-Priority-Encoder
BCD-to-Seven-Segment-Decoder
Binary-to-Excess-3-Code-Converter
Binary-to-Gray-Code-Converter
parity-checker
Two-bit-Wide-8-1-Mux
Logic-Gates
Logic-Gates
AND-Gate
NOT-Gate
OR-Gate
Sequential-Statements
Sequential-Statements
Case-statements
If-generate-Statements
Null-Statements
Process-Statement
Shift-Registers
Shift-Registers
4-bit-shift-register
8-bit-shift-register
RAM
Simple-barrel-shifter
Universal-shift-register
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