4 Bit Substractor :

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity subtr is
	port (A, B : in std_logic_vector(3 downto 0);
	        Q : out std_logic_vector(3 downto 0));
end subtr;

architecture subtr_arch of subtr is
begin
        process (A, B)
	variable TEMP_B : std_logic_vector(3 downto 0);
	begin
		TEMP_B:=not B;
		Q <= A + TEMP_B + '1';
	end process;
end subtr_arch;