Home > VHDL > Concurrent Statements > Component Declarations

5.5 Component Declarations :

Component declaration declare the components used in structural modeling. Component is declared similar to entity. The component is used in component instantiation statement. The component is declared in architecture part of the design. Component clearly shows the pair between entity and architecture. Component also shows the subsystem used in the structural modeling architecture. It is essential that the component should be declared before the component instantiation. Figure shows the component declarations. The syntax is :

Component name_component Port (port_name : mode port_type; Port_name : mode port_type; ……… port_name : mode port_type; end component;

Examples : 3 input NAND Gate

component nand3
	generic (propagation_delay : Time := 5 ns);
	port (a, b, c : in std_logic;
	y : out std_logic);
end component;