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Data Types :

A set of values and a set of operations is called as Data Types. There are nine classes of types in VHDL .

(1) Scalar types (values of these types have no elements),

(2) Composite types (values of these types consist of element values),

(3) Access types (provide access to objects of a given type)

(4) Files (provide access to objects that contain a sequence of values of a given type)

(5) Array Types

(6) Record Types

(7) Predefined VHDL Data Types

(8) Unsupported Data Types

(9) Subtypes

(10) Physical Type

The Syntax of data type is :

type type_name_specify is type_define;

type type_name_specify;

1) Scalar Type :

Scalar type is a type whose values have no elements. The scalar type values cannot contain any composite elements. The Syntax of Scalar Type is :

scalar_type ::= enumeration_type

integer_type

floating_type

physical_type

2) Composite Type :

An object of a composite type is a collection of other objects, called elements. The Syntax of Composite type is,

composite_type ::= array_type | record_type

3) Access Types :

Access type allows to manipulate data, which are created dynamically during simulation.The syntax of access type is :

access_type::=access

subtype_indication

incomplete_type_declation::=type

identifier

4) Array Types :

The array is a composite object, which elements are of the same subtype. The Syntax of Array Type is,

type type_name_define is array (range) of element_type_specify

type type_name_define is array (type range <>) of element_type_specify

Examples :

  type count is array (15 downto 0) of BIT;
  type data_array is array (7 downto 0) of BYTE;

5) Physical Type:

A physical type allows defining measurement units for some physical quantity, like length, time, pressure, capacity, etc. The Syntax of Physical Type is :

  type type_name_specify is range left_bound_specify downto right_bound_specify
  units   primary_unit_name_specify
  secondary_unit_name_specify = number primary_unit_name_specify
  secondary_unit_name_specify = number primary_unit_name_specify
  . . .
  end units type_name_specify

  type type_name_specify is range left_bound_specify downto right_bound_specify
  units   primary_unit_name_specify
  secondary_unit_name_specify = number primary_unit_name_specify
  secondary_unit_name_specify = number primary_unit_name_specify
  . . .
  end units type_name_specify

6) Subtypes :

Subtype declarations are used to define subsets of a type. The Syntax of Subtype is :

subtype_declaration_specify ::= subtype identifier is subtype_indication_specify ;

subtype_indication_specify ::= [ resolution_function_name ] type_mark [ constraint ]

type_mark_specify ::= type_name_specify | subtype_name_specify

constraint_specify ::= range_constraint_specify | index_constraint_specify

Examples :

  subtype count is integer range 0 to 400;
  subtype data_specify is character range '0' to '9';

7) Predefined VHDL Data Types :

VHDL describes specific packages which contain standard set of types and operations.

1 Bit :

The Bit type is from the Standard package has two allowable values: '0' and '1'.

• Example :

  signal D1, D2 : bit;
  . . .
  D1 <= '1';
  D2 <= not D1;

Bit_Vector :

The Bit_Vector type is from the Standard package and has Bit type elements. 

• Example :

  signal Count : Bit_vector(7 downto 0);
  signal test : Bit;
  Count (0) <= '1';
  Count <= '0' & "111000" &  test;
  Count <= ('0', others => '1');
  Count <= Count (6 downto 0) & Count (7);
  Count <= "01110001";

Boolean :

The Boolean type is from the Standard package which has false and true values.

• Example :

  signal test_main : boolean;
  test_main <= true;
  . . .
  if test_main then
  if test_main = true then