The Need for State Machines :

VHDL Coding of FSM : VHDL contains no formal format for finite state machines. A state machine description contains, a state variable, a clock, specification of state transitions, specification of outputs and a reset condition. The clock and reset are to be declared in a PROCESS statement. The output is specified using any concurrent statement. All the state machine elements are specified in a single process. The state variable is used to maintain the state of the circuit and is latched using a clocked process. When the clock edge occurs, the value of the next state is loaded into the registers. If the number of states are not correctly counted for by all possible bit patterns in the state variable the extra states are to be addressed.

State Variables :

The state variable is the name of the signal or variable which is used to define the state of the machine.
(a) The state variableshould be either a signal or a variable.
(b) The state variable should of following types :
BOOLEAN, BIT, STD_ULOGIC, STD_LOGIC
Array of BOOLEAN, BIT_VECTOR, STD_ULOGIC_VECTOR, STD_LOGIC_VECTOR
Predefined enumerated and user defined enumerated.
INTEGER
User defined discrete types
(c) A separate process, or pair of processes are required for each state machine in an architecture.
(d) The state variable should be initialized to a start state.

State Assignment : The CAD tool recognizes and synthesizes a variety of FSMs modeled in VHDL. There are two state assignment categories that are, 1) Explicitly Defined State Assignment and 2) Undefined State Assignment.

Explicitly Defined State Assignment :

In this category we will have to define the state assignments by assigning a discrete value to each state. For example, consider the bellow VHDL code,

PROCESS (clk)
 	VARIABLE stv : INTEGER RANGE 0 TO 1;
 	BEGIN
 	IF clk = '1' THEN
 	CASE stv IS
 	WHEN 0 => output <= '0';
 	stv := 1;
 	WHEN 1 => output <= '1';
 	stv := 0;
 	END CASE;
	END IF;
 	END PROCESS;

Here, the state variable for this state machine is defined in a variable of type integer with two possible values, 0 or 1. The state assignment has been explicitly defined whenever the type of the state variable is, BIT, BIT_VECTOR, INTEGER, STD_LOGIC and STD_ULOGIC_VECTOR.

Undefined State Assignment :

The definition of this category of state machines is that the designer has defined the state variable as an enumerated type and instructs CAD tool as to which type of state assignment is to be done : Binary, One-hot, Random, Gray.

LIBRARY IEEE;
	USE IEEE.STD_LOGIC_1164.ALL;

	ENTITY state_machine IS
	PORT (clk : IN STD_LOGIC;
 	output : OUT STD_LOGIC);
 	END state_machine;

 	ARCHITECTURE rtl OF state_machine IS
 	TYPE state_enum IS (s0, s1);
 	BEGIN
	
 	fsm: PROCESS
 	VARIABLE stv : state_enum := s0;
	BEGIN
	WAIT UNTIL (clk = '1');
	CASE stv IS
	WHEN s0 => output <= '0';
 	stv := s1;
 	WHEN s1 => output <= '1';
 	stv := s0;
 	END CASE;
 	END PROCESS fsm;
	
 	END rtl;