Project Title: HIGH SPEED 4 BIT SFQ MULTIPLIER

Brief Introduction:

2-bit Booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) was made. The Booth encoding method is among the algorithms to own products that are partial. The amount of partial products decreases down seriously to the half set alongside the plus array method with this specific method. The circuit section of the multiplier created using the Booth encoder strategy is within comparison to that designed aided by the AND array method. The proposed modified that is 4-bit encoders are designed Quartus-II. The spot, energy and delay performance of the Booth encoder and modified Booth Encoder have now been analyzed through the production that is simulated implies that modified Booth encoder implemented SFQ multiplier better when put next with Booth encoder that is traditional.

Hardware Details:

• DSP architecture
• Booth encoder
• SFQ multiplier

Software Details:

• MATLAB
• Xilinx
• VHDL

Block Diagram:

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