Project Title: High Speed Multiplier -Accumulator Using SPST

Brief Introduction:

In this task, we proposed a architecture that is MAC for high-speed arithmetic and power that is low. Multiplication occurs frequently in finite impulse reaction filters, fast Fourier transforms, discrete cosine transforms, convolution, along side other essential DSP and multimedia kernels. The prospective with this multiplier that is accumulator that is good MAC is obviously to supply a physically compact, good rate and low power chip that is eating. This might be an easy method that is decrease that is good effective energy that is the true secret of total energy dissipation to truly save significant energy utilization of a VLSI design. In this project, we propose a better expense MAC adopting the SPST that is approach that is modern utilizing. This multiplier and accumulator is manufactured by equipping the Spurious Power Suppression Technique (SPST) on a modified Booth encoder which is handled in the form of a detection item using an AND gate. The modified booth encoder will really reduce the degree of partial products and services created by method of a component of 2. The SPST adder will avoid the addition that is minimise that is undesired power dissipation that is switching.

Hardware Details:

• Booth encoder
• FPGA

Software Details:

• Xilinx
• VHDL

Block Diagram:

For more details