Project Title: DDR SDRAM CONTROLLER

Brief Introduction:

DDR SDRAM (Double Data Rate Synchronously Dynamic RAM) is SDRAM with 2n prefetch architecture. DDR SDRAM many frequently utilized in several application that is embedded indication processing, networking, image/video processing etc which need many others cheap and fast memory. The memory controller takes commands individual that is using is local and translates them to your command sequences necessary by DDR SDRAM devices. Precisely how over you shall find challenges in their controller design those are arising to their right requirement much as regular procedure that is memory that is procedure that is refresh appropriate active and precharge command etc. The idea and commands of DDR SDRAM controller design are explained in this paper. The operations of DDR SDRAM controller are recognized through Verilog HDL .This proposed architecture design of DDR SDRAM controller is utilized as ip core into any FPGA based embedded system requirement that is having of procedure.

Hardware Details:

• DDR SDRAM Controller
• Micron DDR Memory model
• JEDEC Standard

Software Details:

• Icarus Verilog
• Altera Quartus II 9.0.
• Verilog HDL

Block Diagram:

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