Project Title: Low Power Video Compression Achitecture

Brief Introduction:

This project presents a solution to lessen the calculation and memory access for variable block size movement estimation pixel truncation that is utilizing. Past work has dedicated to pixel truncation that is implementing using a size that is pixels which are fixed-block. Nonetheless, pixel truncation doesn't provide outcomes which can be satisfactory smaller block partitions. In this project, assess the effect of truncating pixels for smaller block partitions and propose a method to improve the framework forecast. Our method is able to reduce steadily the computation and that is total memory access in comparison with traditional method that is full-search somewhat image quality that is degrading. The proposed architectures are able to save up to 53% power set alongside the with original data arrangement Mainstream architecture that is full-search.

Hardware Details:

• motion compensator
• transform coder,
• deblocking filter
• entropy coder
• integer transform
• inverse integer transform
• quantizer

Software Details:

• UMC 0.13μm CMOS library.
• Verilog-XL
• Power Compiler

Block Diagram:

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