Home > vlsi projects > Proj 51 High Speed Floating Point Addition and Subtraction
Project Title: High Speed Floating Point Addition and Subtraction
Brief Introduction:
A leading-zero that is completely new logic for high-speed floating-point subtraction and addition is proposed. The pre-decoding for normalization simultaneously with addition for the significant is completed in this logic. Shift operation of normalization in parallel with the procedure that is rounding also performed. The employment of easy algebra that is Boolean the logic that is proposed be produced of a simple CMOS circuit. The purpose that's floating play an component that is essential the present day microprocessors. The wait and energy usage should be optimized getting an design that is efficient. The normalization may be the procedure that is primary of point information course, the manufacturing of the point that is floating must be normalized according to the IEEE 754 format. The normalization involves leading zero countertop and a normalization shifter. A number one zero anticipator is used to enhance the calculation speed generally in most the situations. A few casino chips which are floating-point in manufacturing have used the this approach to cut their wait time right back. The logic is required to anticipate the pseudo outcome, the clear and thorough summary associated with the response that is clear is efficient be positioned.
Hardware Details:
* Spartan 3E family device XC3S500E package FG320 with speed grade -5.
* Leading Zero Anticipation Method
Software Details:
- Verilog HDL
Block Diagram:
