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Project Title: Low Power Adder Compressors
Brief Introduction:
This project presents two adder compressors architectures managing high-speed and power that is low. Adder compressors are acclimatized to implement arithmetic circuits such as for instance multipliers and sign that is units which are electronic just like the Fast Fourier Transform (FTT). To cope with the aim of high-speed and energy that is low it truly is well known That optimization efforts should be found in abstraction levels which are many. In this project combined optimizations at logic, electric and degree that is real. The circuit is optimized with the use of multiplexers instead of during the logic degree XOR gates to minimize delay, energy and area. This work presents an architecture that at the particular level that is electrical generate the XOR and XNOR signals simultaneously, this minimize issues that are interior that is thus effective well. Last but not least during the level that is real and design that is automated tool (ASTRAN) is required to make the adder compressors designs. This product has shown to lessen power delay and usage being a total result of the smaller input capacitances associated with the gates which are complex compared to designs that are manual-designed.
Hardware Details:
* 3-2 Compressor
- 4-2 compressors
Software Details:
* Automatic Layout Generation using ASTRAN
- HSPICE simulator
Block Diagram:
