Project Title: Face Detection System Using Haar Classifiers

Brief Introduction:

This project presents a architecture that is face that is hardware system that is formulated AdaBoost algorithm using Haar features. We give a conclusion for gear design techniques image that is including, key image generation, pipelined processing because well as classifier, and processing that is synchronous which are numerous accelerate the speed that is processing of face detection system. Additionally we discuss the optimization regarding the proposed architecture which is often scalable for configurable services and products with adjustable resources. The proposed architecture for face detection is completed Verilog that is usage that is making of found in Xilinx Virtex-5 FPGA. Their performance is determined and weighed against some type of computer pc software execution that can be compared. We reveal about 35 times enhance of system performance through the applying that is whole execution that is comparable.

Hardware Details:

• Xilinx Virtex-5 FPGA

Software Details:

• Verilog HDL
• OpenCV

Block Diagram:

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